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DAC
1996
ACM
13 years 11 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
GIS
2005
ACM
14 years 8 months ago
Dimension-refined topological predicates
Topological predicates, as derived from the 9-intersection model, have been widely recognized in GIS, spatial database systems, and many other geo-related disciplines. They are ba...
Mark McKenney, Alejandro Pauly, Reasey Praing, Mar...
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 4 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 26 days ago
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated
Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the CAD tools to manipulate the designs within the tools. These f...
Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupt...
RTS
2006
176views more  RTS 2006»
13 years 7 months ago
Verifying distributed real-time properties of embedded systems via graph transformations and model checking
Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. C...
Gabor Madl, Sherif Abdelwahed, Douglas C. Schmidt