816 search results - page 15 / 164 » Automating Verification by Functional Abstraction at the Sys... |
CASCON
2001
13 years 10 months ago
2001
Automated verification tools vary widely in the types of properties they are able to analyze, the complexity of their algorithms, and the amount of necessary user involvement. In ...
TPHOL
1998
IEEE
14 years 1 months ago
1998
IEEE
Abstract. Over the last decade, the increasing demand for the validation of safety critical systems lead to the development of domain-specific programming languages (e.g. synchrono...
DSD
2004
IEEE
14 years 22 days ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
FPL
2006
Springer
14 years 20 days ago
2006
Springer
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
AHS
2007
IEEE
14 years 1 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...