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» Automating software feature verification
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SPLC
2010
13 years 5 months ago
Stratified Analytic Hierarchy Process: Prioritization and Selection of Software Features
Product line engineering allows for the rapid development of variants of a domain specific application by using a common set of reusable assets often known as core assets. Variabil...
Ebrahim Bagheri, Mohsen Asadi, Dragan Gasevic, Sam...
TPHOL
1994
IEEE
13 years 11 months ago
Trustworthy Tools for Trustworthy Programs: A Verified Verification Condition Generator
Verification Condition Generator (VCG) tools have been effective in simplifying the task of proving programs correct. However, in the past these VCG tools have in general not thems...
Peter V. Homeier, David F. Martin
DAC
2006
ACM
14 years 7 months ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...
ASE
2005
103views more  ASE 2005»
13 years 6 months ago
Component Verification with Automatically Generated Assumptions
Abstract. Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. The typical approach to verifying propertie...
Dimitra Giannakopoulou, Corina S. Pasareanu, Howar...
DAC
2007
ACM
14 years 7 months ago
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This pap...
Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang