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MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
14 years 1 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
ASPLOS
2010
ACM
14 years 1 months ago
Probabilistic job symbiosis modeling for SMT processor scheduling
Symbiotic job scheduling boosts simultaneous multithreading (SMT) processor performance by co-scheduling jobs that have ‘compatible’ demands on the processor’s shared resour...
Stijn Eyerman, Lieven Eeckhout
INFOCOM
2003
IEEE
14 years 1 months ago
Static and Dynamic Analysis of the Internet's Susceptibility to Faults and Attacks
— We analyze the susceptibility of the Internet to random faults, malicious attacks, and mixtures of faults and attacks. We analyze actual Internet data, as well as simulated dat...
Seung-Taek Park, Alexy Khrabrov, David M. Pennock,...
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 29 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
MASCOTS
2010
13 years 9 months ago
PUD-LRU: An Erase-Efficient Write Buffer Management Algorithm for Flash Memory SSD
Flash memory SSDs pose a well-known challenge, that is, the erase-before-write problem. Researchers try to solve this inherent problem from two different angles by either designing...
Jian Hu, Hong Jiang, Lei Tian, Lei Xu