819 search results - page 152 / 164 » BSN Simulator: Optimizing Application Using System Level Sim... |
114
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CODES
2005
IEEE
15 years 8 months ago
2005
IEEE
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
156
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DAC
2006
ACM
15 years 4 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
116
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ISCA
2009
IEEE
15 years 9 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
169
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HIPEAC
2011
Springer
14 years 1 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
122
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MOBICOM
2004
ACM
15 years 7 months ago
2004
ACM
Topology control algorithms usually reduce the number of links in a wireless network, which in turn decreases the degree of connectivity. The resulting network topology is more su...