233 search results - page 17 / 47 » Balance Testing of Logic Circuits |
VTS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
PARLE
1987
1987
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
13 years 11 months ago
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
CHES
2007
Springer
14 years 1 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
ICES
2000
Springer
13 years 11 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
ICISC
2009
13 years 5 months ago
2009
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...