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» Balance Testing of Logic Circuits
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ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 11 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
14 years 25 days ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
13 years 11 months ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
ITC
1997
IEEE
80views Hardware» more  ITC 1997»
13 years 11 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...
DAC
2005
ACM
14 years 8 months ago
Structural search for RTL with predicate learning
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting...