Sciweavers

233 search results - page 44 / 47
» Balance Testing of Logic Circuits
Sort
View
DAC
2010
ACM
13 years 12 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
ICTAI
2002
IEEE
14 years 1 months ago
A Clustering Based Approach to Efficient Image Retrieval
This paper addresses the issue of effective and efficient content based image retrieval by presenting a novel indexing and retrieval methodology that integrates color, texture, an...
Ruofei Zhang, Zhongfei Zhang
CHES
2005
Springer
96views Cryptology» more  CHES 2005»
14 years 2 months ago
The "Backend Duplication" Method
Abstract. Several types of logic gates suitable for leakage-proof computations have been put forward [1,2,3,4]. This paper describes a method, called “backend duplication” to a...
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu,...
DAC
2009
ACM
14 years 9 months ago
Improving testability and soft-error resilience through retiming
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 3 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...