55 search results - page 6 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
CDES
2009
13 years 8 months ago
2009
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
IJNM
2008
13 years 7 months ago
2008
In this article we examine the architecture of an entity used for automatic management and provisioning of resources for DiffServ networks. We examine the existing literature and ...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
FCCM
2003
IEEE
14 years 27 days ago
2003
IEEE
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...