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WMPI
2004
ACM
14 years 4 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
IC
2003
14 years 7 days ago
An Adaptive Hierarchy Management System for Web Caches
A group of web caches can be organized into a cooperative hierarchy where a search for a requested object is performed among the cooperating peer caches before the object request ...
Pranav A. Desai, Jaspal Subhlok
DAC
2012
ACM
12 years 1 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
MASCOTS
2001
14 years 7 days ago
Simulation Evaluation of a Heterogeneous Web Proxy Caching Hierarchy
This paper uses trace-driven simulations to evaluate the performance of different cache management techniques for multi-level Web proxy caching hierarchies. In particular, the exp...
Mudashiru Busari, Carey L. Williamson
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 4 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...