271 search results - page 33 / 55 » Bandwidth-Friendly Cache Hierarchy |
ISCA
2009
IEEE
14 years 4 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
SIGMETRICS
1996
ACM
14 years 2 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
ISCA
1993
IEEE
14 years 2 months ago
1993
IEEE
The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with...
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
— An effectively designed and efficiently used memory hierarchy, composed of scratch-pads or cache, is seen today as the key to obtaining energy and performance gains in data-do...