271 search results - page 37 / 55 » Bandwidth-Friendly Cache Hierarchy |
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
CASES
2010
ACM
13 years 7 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
MICRO
2000
IEEE
14 years 2 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
SIGMETRICS
1992
ACM
14 years 1 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...