271 search results - page 4 / 55 » Bandwidth-Friendly Cache Hierarchy |
DATE
2004
IEEE
14 years 1 months ago
2004
IEEE
ISCAPDCS
2004
13 years 11 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
GLVLSI
2008
IEEE
14 years 4 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
RTSS
2008
IEEE
14 years 4 months ago
2008
IEEE
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...