130 search results - page 21 / 26 » Battery-Powered Digital CMOS Design |
CSREAESA
2003
13 years 11 months ago
2003
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
ICIP
2006
IEEE
14 years 11 months ago
2006
IEEE
Compressive Sensing is an emerging field based on the revelation that a small group of non-adaptive linear projections of a compressible signal contains enough information for rec...
ISCAS
2008
IEEE
14 years 4 months ago
2008
IEEE
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...
ISCAS
2011
IEEE
13 years 1 months ago
2011
IEEE
—A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an a...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...