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154
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods an...
165
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
158
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SIGSOFT
2005
ACM
16 years 6 months ago
2005
ACM
In unit testing, a program is decomposed into units which are collections of functions. A part of unit can be tested by generating inputs for a single entry function. The entry fu...
204
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CADE
2007
Springer
16 years 6 months ago
2007
Springer
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
136
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ICCAD
2006
IEEE
16 years 2 months ago
2006
IEEE
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...