Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
The research on real-time scheduling has mostly focused on the development of algorithms that allows to test whether the constraints imposed on the task execution (often expressed ...
A detailed implementation of the Tabu Search (TS) algorithm for computer-aided molecular design (CAMD) of transition metal catalysts is presented in this paper. Previous CAMD rese...
Bao Lin, Sunitha Chavali, Kyle V. Camarda, David C...