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ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
13 years 11 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
CEC
2009
IEEE
14 years 2 months ago
Semantically driven mutation in genetic programming
—Using semantic analysis, we present a technique known as semantically driven mutation which can explicitly detect and apply behavioural changes caused by the syntactic changes i...
Lawrence Beadle, Colin G. Johnson
ICCAD
1999
IEEE
79views Hardware» more  ICCAD 1999»
13 years 12 months ago
Improved interconnect sharing by identity operation insertion
This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analys...
Dirk Herrmann, Rolf Ernst
OOPSLA
2007
Springer
14 years 1 months ago
Statistically rigorous java performance evaluation
Java performance is far from being trivial to benchmark because it is affected by various factors such as the Java application, its input, the virtual machine, the garbage collect...
Andy Georges, Dries Buytaert, Lieven Eeckhout
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
14 years 2 months ago
Signal Probability Based Statistical Timing Analysis
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
Bao Liu