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ISLPED
1995
ACM
80views Hardware» more  ISLPED 1995»
14 years 1 months ago
Techniques for fast circuit simulation applied to power estimation of CMOS circuits
We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses s...
Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. K...
ISSS
1995
IEEE
121views Hardware» more  ISSS 1995»
14 years 1 months ago
A comprehensive estimation technique for high-level synthesis
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...
Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min X...
NIPS
1998
13 years 11 months ago
A High Performance k-NN Classifier Using a Binary Correlation Matrix Memory
This paper presents a novel and fast k-NN classifier that is based on a binary CMM (Correlation Matrix Memory) neural network. A robust encoding method is developed to meet CMM in...
Ping Zhou, Jim Austin, John Kennedy
ICCAD
2010
IEEE
166views Hardware» more  ICCAD 2010»
13 years 7 months ago
Low-power clock trees for CPUs
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
Dongjin Lee, Myung-Chul Kim, Igor L. Markov
CASES
2008
ACM
13 years 11 months ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...