Sciweavers

436 search results - page 54 / 88
» Benchmarking and hardware implementation of JPEG-LS
Sort
View
ICCAD
1994
IEEE
91views Hardware» more  ICCAD 1994»
13 years 12 months ago
A loosely coupled parallel algorithm for standard cell placement
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
Wern-Jieh Sun, Carl Sechen
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
13 years 11 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
13 years 11 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
SIGMETRICS
1992
ACM
145views Hardware» more  SIGMETRICS 1992»
13 years 11 months ago
Analysis of the Generalized Clock Buffer Replacement Scheme for Database Transaction Processing
The CLOCK algorithm is a popular buffer replacement algorithm becauseof its simplicity and its ability to approximate the performance of the Least Recently Used (LRU) replacement ...
Victor F. Nicola, Asit Dan, Daniel M. Dias
CAV
2007
Springer
164views Hardware» more  CAV 2007»
13 years 11 months ago
SAT-Based Compositional Verification Using Lazy Learning
Abstract. A recent approach to automated assume-guarantee reasoning (AGR) for concurrent systems relies on computing environment assumptions for components using the L algorithm fo...
Nishant Sinha, Edmund M. Clarke