436 search results - page 67 / 88 » Benchmarking and hardware implementation of JPEG-LS |
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
CAV
2004
Springer
14 years 1 months ago
2004
Springer
The logic of equality with uninterpreted functions (EUF) and its extensions have been widely applied to processor verification, by means of a large variety of progressively more s...
PPSN
2004
Springer
14 years 1 months ago
2004
Springer
Evolving large phenotypes remains nowadays a problem due to the combinatorial explosion of the search space. Seeking better scalability and inspired by the development of biologica...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
ISLPED
2003
ACM
14 years 28 days ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...