686 search results - page 25 / 138 » Benchmarking cerebellar control |
WCNC
2010
IEEE
13 years 11 months ago
2010
IEEE
—Controlled mobile helper nodes called data ferries have recently been proposed to bridge communications between disconnected nodes in a delay-tolerant manner. While existing wor...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
HPCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...