686 search results - page 69 / 138 » Benchmarking cerebellar control |
138
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IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
130
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ISQED
2010
IEEE
15 years 9 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
136
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FPL
2009
Springer
15 years 9 months ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
140
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ATS
2000
IEEE
15 years 9 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
130
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ASPLOS
2000
ACM
15 years 9 months ago
2000
ACM
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...