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AAAI
2010
13 years 8 months ago
Multi-Instance Dimensionality Reduction
Multi-instance learning deals with problems that treat bags of instances as training examples. In single-instance learning problems, dimensionality reduction is an essential step ...
Yu-Yin Sun, Michael K. Ng, Zhi-Hua Zhou
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 1 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 4 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
IEEECIT
2010
IEEE
13 years 5 months ago
Superblock-Based Source Code Optimizations for WCET Reduction
—Superblocks represent regions in a program code that consist of multiple basic blocks. Compilers benefit from this structure since it enables optimization across block boundari...
Paul Lokuciejewski, Timon Kelter, Peter Marwedel