This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Abstract. This paper describes the design and implementation of a practical parallel algorithm for Delaunay triangulation that works well on general distributions. Although there h...
Guy E. Blelloch, Jonathan C. Hardwick, Gary L. Mil...
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
Future wireless sensor networks (WSNs) are projected to run multiple applications in the same network infrastructure. While such multi-application WSNs (MA-WSNs) are economically ...
Weijia Li, Yu Du, Youtao Zhang, Bruce Childers, Pi...