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SLIP
2009
ACM
14 years 3 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...
ALGORITHMICA
1999
141views more  ALGORITHMICA 1999»
13 years 8 months ago
Design and Implementation of a Practical Parallel Delaunay Algorithm
Abstract. This paper describes the design and implementation of a practical parallel algorithm for Delaunay triangulation that works well on general distributions. Although there h...
Guy E. Blelloch, Jonathan C. Hardwick, Gary L. Mil...
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 9 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
ASPDAC
2004
ACM
119views Hardware» more  ASPDAC 2004»
14 years 2 months ago
A fast congestion estimator for routing with bounded detours
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang
EUC
2008
Springer
13 years 10 months ago
Adaptive Buffer Management for Efficient Code Dissemination in Multi-Application Wireless Sensor Networks
Future wireless sensor networks (WSNs) are projected to run multiple applications in the same network infrastructure. While such multi-application WSNs (MA-WSNs) are economically ...
Weijia Li, Yu Du, Youtao Zhang, Bruce Childers, Pi...