142 search results - page 6 / 29 » Better than a petaflop: The power of efficient experimental ... |
ISCAS
2003
IEEE
14 years 25 days ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
ICIP
2003
IEEE
14 years 9 months ago
2003
IEEE
Wavemesh is a powerful scheme for 3D triangular mesh processing. In sharp contrast with other approaches using wavelets for mesh compression which apply only to meshes having subd...
AMAI
2005
Springer
13 years 7 months ago
2005
Springer
We consider auction design in a setting with costly preference elicitation. Well designed auctions can help to avoid unnecessary elicitation while determining efficient allocations...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...