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ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
13 years 11 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 2 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
TASE
2007
IEEE
14 years 1 months ago
Model Checking Networked Programs in the Presence of Transmission Failures
Software model checkers work directly on single-process programs, but not on multiple processes. Conversion of processes into threads, combined with a network model, allows for mo...
Cyrille Artho, Christian Sommer 0002, Shinichi Hon...
GROUP
2003
ACM
14 years 22 days ago
Text chat in action
Synchronous text communication is becoming recognized as a valuable workplace communication medium yet some studies of group text chat indicate that its properties can lead to int...
Jacki O'Neill, David Martin
IUI
2003
ACM
14 years 22 days ago
Summarizing archived discussions: a beginning
This paper describes an approach to digesting threads of archived discussion lists by clustering messages into approximate topical groups, and then extracting shorter overviews, a...
Paula S. Newman, John C. Blitzer