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COMGEO
2011
ACM
13 years 5 months ago
Characterizations of restricted pairs of planar graphs allowing simultaneous embedding with fixed edges
A set of planar graphs share a simultaneous embedding if they can be drawn on the same vertex set V in the Euclidean plane without crossings between edges of the same graph. Fixed ...
J. Joseph Fowler, Michael Jünger, Stephen G. ...
ICMCS
2005
IEEE
115views Multimedia» more  ICMCS 2005»
14 years 3 months ago
Detector Design for Parametric Speech Watermarking
Parametric watermarking is effected by modifying the linear predictor coefficients of speech. In this work, the parameter noise is analyzed when watermarked speech is subjected t...
Aparna Gurijala, John R. Deller Jr.
EVOW
2004
Springer
14 years 3 months ago
Disjoint Sum of Product Minimization by Evolutionary Algorithms
Recently, an approach has been presented to minimize Disjoint Sumof-Products (DSOPs) based on Binary Decision Diagrams (BDDs). Due to the symbolic representation of cubes for larg...
Nicole Drechsler, Mario Hilgemeier, Görschwin...
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
14 years 3 months ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu
DAC
1996
ACM
14 years 2 months ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant