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CASES
2008
ACM
13 years 9 months ago
Control flow optimization in loops using interval analysis
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau
IESS
2007
Springer
156views Hardware» more  IESS 2007»
14 years 1 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
RTAS
2005
IEEE
14 years 1 months ago
VPN Gateways over Network Processors: Implementation and Evaluation
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, ...
Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Yuan-C...
CODES
2006
IEEE
13 years 11 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
LCTRTS
2009
Springer
14 years 2 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava