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ICIP
2000
IEEE
14 years 10 months ago
Combined Spatial and Subband Block Coding of Images
This paper describes a low-memory cache efficient Hybrid Block Coder (HBC) for images in which an image subband decomposition is partitioned into a combination of spatial blocks a...
Frederick W. Wheeler, William A. Pearlman
CODES
2001
IEEE
14 years 8 days ago
Towards effective embedded processors in codesigns: customizable partitioned caches
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
Peter Petrov, Alex Orailoglu
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
14 years 9 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
CF
2010
ACM
13 years 11 months ago
Global management of cache hierarchies
Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to...
Mohamed Zahran, Sally A. McKee
CAL
2002
13 years 8 months ago
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
Ann Gordon-Ross, Susan Cotterell, Frank Vahid