613 search results - page 21 / 123 » Block cache for embedded systems |
MICRO
1997
IEEE
14 years 25 days ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
FPGA
1999
ACM
14 years 28 days ago
1999
ACM
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition...
HIPEAC
2010
Springer
14 years 5 months ago
2010
Springer
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...