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IPPS
2010
IEEE
13 years 6 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
IEEEPACT
2009
IEEE
14 years 3 months ago
Using Aggressor Thread Information to Improve Shared Cache Management for CMPs
—Shared cache allocation policies play an important role in determining CMP performance. The simplest policy, LRU, allocates cache implicitly as a consequence of its replacement ...
Wanli Liu, Donald Yeung
IJON
2006
165views more  IJON 2006»
13 years 8 months ago
Design and basic blocks of a neuromorphic VLSI analogue vision system
: In this paper we present a complete neuromorphic image processing system and we report the development of an integrated CMOS low-power circuit to test the feasibility of its diff...
Jordi Cosp, Jordi Madrenas, Daniel Fernánde...
ASIASIM
2004
Springer
14 years 2 months ago
LSTAFF: System Software for Large Block Flash Memory
Abstract. Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption...
Tae-Sun Chung, Dong-Joo Park, Yeonseung Ryu, Sugwo...
ISCA
2002
IEEE
68views Hardware» more  ISCA 2002»
14 years 1 months ago
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras