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RTSS
2008
IEEE
14 years 2 months ago
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
Integrating COTS components in critical real-time systems is challenging. In particular, we show that the interference between cache activity and I/O traffic generated by COTS pe...
Rodolfo Pellizzoni, Bach Duy Bui, Marco Caccamo, L...
ECMDAFA
2010
Springer
138views Hardware» more  ECMDAFA 2010»
13 years 5 months ago
A UML 2.0 Profile to Model Block Cipher Algorithms
Abstract. Current mobile digital communication systems must implement rigorous operations to guarantee high levels of confidentiality and integrity during transmission of critical ...
Tomás Balderas-Contreras, Gustavo Rodr&iacu...
DATE
2000
IEEE
101views Hardware» more  DATE 2000»
14 years 4 days ago
Memory Arbitration and Cache Management in Stream-Based Systems
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
Françoise Harmsze, Adwin H. Timmer, Jef L. ...
WCET
2010
13 years 5 months ago
Bounding the Effects of Resource Access Protocols on Cache Behavior
The assumption of task independence has long been consubstantial with the formulation of many schedulability analysis techniques. That assumption is evidently advantageous for the...
Enrico Mezzetti, Marco Panunzio, Tullio Vardanega
OSDI
1996
ACM
13 years 9 months ago
A Trace-Driven Comparison of Algorithms for Parallel Prefetching and Caching
High-performance I/O systems depend on prefetching and caching in order to deliver good performance to applications. These two techniques have generally been considered in isolati...
Tracy Kimbrel, Andrew Tomkins, R. Hugo Patterson, ...