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EUROMICRO
1999
IEEE
14 years 1 days ago
A Selective Compressed Memory System by On-Line Data Decompressing
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
CN
2002
77views more  CN 2002»
13 years 7 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...
JTRES
2010
ACM
13 years 8 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
CHI
2004
ACM
14 years 8 months ago
Z-Tiles: building blocks for modular, pressure-sensing floorspaces
A new interactive floorspace has been developed which uses modular nodes connected together to create a pressuresensitive area of varying size and shape, giving it the potential t...
Bruce Richardson, Joseph A. Paradiso, Krispin Leyd...