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ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
13 years 12 months ago
Using Prediction to Accelerate Coherence Protocols
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
Shubhendu S. Mukherjee, Mark D. Hill
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 2 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
POPL
2009
ACM
14 years 8 months ago
Modular code generation from synchronous block diagrams: modularity vs. code size
We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the emb...
Roberto Lublinerman, Christian Szegedy, Stavros Tr...
IDEAS
2003
IEEE
117views Database» more  IDEAS 2003»
14 years 1 months ago
A Multi-Resolution Block Storage Model for Database Design
We propose a new storage model called MBSM (Multiresolution Block Storage Model) for laying out tables on disks. MBSM is intended to speed up operations such as scans that are typ...
Jingren Zhou, Kenneth A. Ross
JPDC
2007
60views more  JPDC 2007»
13 years 7 months ago
The impact of wrong-path memory references in cache-coherent multiprocessor systems
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...