Sciweavers

613 search results - page 7 / 123
» Block cache for embedded systems
Sort
View
CF
2004
ACM
14 years 10 days ago
Reducing traffic generated by conflict misses in caches
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
Pepijn J. de Langen, Ben H. H. Juurlink
CSREAESA
2007
13 years 10 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
14 years 2 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
DAC
2003
ACM
14 years 1 months ago
Improved indexing for cache miss reduction in embedded systems
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
Tony Givargis
PPAM
2005
Springer
14 years 2 months ago
A New Diagonal Blocking Format and Model of Cache Behavior for Sparse Matrices
Algorithms for the sparse matrix-vector multiplication (shortly SpM×V ) are important building blocks in solvers of sparse systems of linear equations. Due to matrix sparsity, the...
Pavel Tvrdík, Ivan Simecek