16 search results - page 2 / 4 » Block-level 3D IC design with through-silicon-via planning |
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
ICCAD
2009
IEEE
13 years 4 months ago
2009
IEEE
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
DAC
2009
ACM
14 years 7 months ago
2009
ACM
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
ISPD
2011
ACM
12 years 9 months ago
2011
ACM
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...