46 search results - page 2 / 10 » Boolean Satisfiability and Equivalence Checking Using Genera... |
CCL
1994
Springer
13 years 11 months ago
1994
Springer
Abstract. We compare two prominent decision procedures for propositional logic: Ordered Binary Decision Diagrams (obdds) and the DavisPutnam procedure. Experimental results indicat...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
CAV
1993
Springer
13 years 11 months ago
1993
Springer
Abstract. We describe the implementation, within ALDEBARAN of an algorithmic method allowing the generation of a minimal labeled transition rom an abstract model ; this minimality ...