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ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
14 years 23 days ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
13 years 6 months ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...
ICFP
2012
ACM
11 years 10 months ago
Nested data-parallelism on the gpu
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
Lars Bergstrom, John H. Reppy
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
13 years 11 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf
IUI
2000
ACM
13 years 12 months ago
Using annotated video as an information retrieval interface
The ability to deliver appropriate information to learners at the most appropriate time is an essential component of good instruction. In the best learning environments, this info...
Andrew S. Gordon