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DAC
2010
ACM
13 years 11 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
KDD
2010
ACM
235views Data Mining» more  KDD 2010»
13 years 11 months ago
New perspectives and methods in link prediction
This paper examines important factors for link prediction in networks and provides a general, high-performance framework for the prediction task. Link prediction in sparse network...
Ryan Lichtenwalter, Jake T. Lussier, Nitesh V. Cha...
CAV
2000
Springer
187views Hardware» more  CAV 2000»
13 years 11 months ago
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
Poul Frederick Williams, Armin Biere, Edmund M. Cl...
IPCO
2007
108views Optimization» more  IPCO 2007»
13 years 9 months ago
Robust Combinatorial Optimization with Exponential Scenarios
Following the well-studied two-stage optimization framework for stochastic optimization [15, 18], we study approximation algorithms for robust two-stage optimization problems with ...
Uriel Feige, Kamal Jain, Mohammad Mahdian, Vahab S...
SODA
2004
ACM
121views Algorithms» more  SODA 2004»
13 years 9 months ago
A characterization of easily testable induced subgraphs
Let H be a fixed graph on h vertices. We say that a graph G is induced H-free if it does not contain any induced copy of H. Let G be a graph on n vertices and suppose that at leas...
Noga Alon, Asaf Shapira