LUT-based FPGA technology mapping for reliability

As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using a scalable overlapping window-based method called DCOW (Don't-care Computation with Overlapping Windows), which allows for accurate and efficient don’t-care lower bound calculations. This new windowing technique can approximate the complete don’t cares within 2.34%, and can be used for many logic synthesis operations. In particular, we apply DCOW to our FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher s...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Jason Cong, Kirill Minkovich
• Keywords: Computer Architecture, DAC 2010, Error Analysis, Lookup Table, Possible Faults