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VTS
2007
IEEE
135views Hardware» more  VTS 2007»
14 years 1 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
LCTRTS
2001
Springer
13 years 11 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
ISPD
2000
ACM
126views Hardware» more  ISPD 2000»
13 years 11 months ago
A practical clock tree synthesis for semi-synchronous circuits
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui,...
CVRMED
1997
Springer
13 years 11 months ago
Geometric constraint analysis and synthesis: methods for improving shape-based registration accuracy
Shape-based registration is a process for estimating the transformation between two shape representations of an object. It is used in many image-guided surgical systems to establis...
David A. Simon, Takeo Kanade
RTSS
2008
IEEE
14 years 1 months ago
Synthesis of Optimal Interfaces for Hierarchical Scheduling with Resources
This paper presents algorithms that (1) facilitate systemindependent synthesis of timing-interfaces for subsystems and (2) system-level selection of interfaces to minimize CPU loa...
Insik Shin, Moris Behnam, Thomas Nolte, Mikael Nol...