1343 search results - page 29 / 269 » Bounded-lifetime integrated circuits |
ICCAD
1997
IEEE
14 years 20 days ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
DAC
2010
ACM
14 years 11 days ago
2010
ACM
Carbon Nanotubes (CNTs) are grown using chemical synthesis, and the exact positioning and chirality of CNTs are very difficult to control. As a result, “small-width” Carbon Na...
JOCN
2010
13 years 6 months ago
2010
■ Although many examples exist for shared neural representations of self and other, it is unknown how such shared representations interact with the rest of the brain. Furthermor...
VTS
2002
IEEE
14 years 1 months ago
2002
IEEE
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...