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ISCAS
2008
IEEE
95views Hardware» more  ISCAS 2008»
14 years 2 months ago
Wireless neural signal acquisition with single low-power integrated circuit
—We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-µm 2P3M BiCMOS process, ...
Reid R. Harrison, Ryan J. Kier, Bradley Greger, Fl...
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
14 years 2 months ago
Thermally robust clocking schemes for 3D integrated circuits
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...
DELTA
2002
IEEE
14 years 1 months ago
Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
Richard J. Blaikie, Maan M. Alkaisi, Steven M. Dur...
INTEGRATION
2008
89views more  INTEGRATION 2008»
13 years 8 months ago
Exact ESCT minimization for functions of up to six input variables
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
INTEGRATION
2008
101views more  INTEGRATION 2008»
13 years 8 months ago
An efficient terminal and model order reduction algorithm
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...