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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
13 years 11 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
DAMON
2007
Springer
14 years 1 months ago
Architectural characterization of XQuery workloads on modern processors
As XQuery rapidly emerges as the standard for querying XML documents, it is very important to understand the architectural characteristics and behaviors of such workloads. A lot o...
Rubao Lee, Bihui Duan, Taoying Liu
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
13 years 11 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 13 days ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
ISCA
2007
IEEE
103views Hardware» more  ISCA 2007»
14 years 1 months ago
Ginger: control independence using tag rewriting
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
Andrew D. Hilton, Amir Roth