Sciweavers

131 search results - page 19 / 27
» Bringing High-Performance Reconfigurable Computing to Exact ...
Sort
View
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 11 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
DAC
2005
ACM
13 years 9 months ago
Circuit optimization using statistical static timing analysis
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladi...
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
14 years 1 months ago
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
Edwin Rijpkema, Kees G. W. Goossens, Andrei Radule...
SIGOPS
2010
144views more  SIGOPS 2010»
13 years 6 months ago
The case for a versatile storage system
Storage systems in emerging large-scale (a.k.a. peta-scale) computing systems often introduce a performance or scalability bottleneck. To deal with these limitations we propose a ...
Samer Al-Kiswany, Abdullah Gharaibeh, Matei Ripean...
DAC
2005
ACM
14 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo