Circuit optimization using statistical static timing analysis

In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is difficult to capture the quality of a distribution with a single metric. Hence, we first introduce a new objective function that provides an effective measure for the quality of a delay distribution for both ASIC and high performance designs. We then propose an efficient and exact sensitivity based pruning algorithm based on a newly proposed theory of perturbation bounds. A heuristic approach for sensitivity computation which relies on efficient computation of statistical slack is then introduced. Finally, we show how the pruning and statistical slack based approaches can be combined to obtain nearly identical results compared with the brute-force approach but with an average run-time improvement of up to 89x. We also compare the optimization results against that of a deterministic optimizer and show an improvem...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
• Keywords: Circuit Delay, Circuit Delay Distribution, Computer Architecture, DAC 2005, Delay Distribution