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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 2 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 2 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
WCNC
2008
IEEE
14 years 2 months ago
Proportional Fair Scheduling: Analytical Insight under Rayleigh Fading Environment
—This paper provides analytical expressions to evaluate the performance of a random access wireless network in terms of user throughput and network throughput, subject to the con...
Erwu Liu, Kin K. Leung
BIBE
2007
IEEE
162views Bioinformatics» more  BIBE 2007»
14 years 2 months ago
An Investigation into the Feasibility of Detecting Microscopic Disease Using Machine Learning
— The prognosis for many cancers could be improved dramatically if they could be detected while still at the microscopic disease stage. We are investigating the possibility of de...
Mary Qu Yang, Jack Y. Yang
CCGRID
2007
IEEE
14 years 2 months ago
Performance Evaluation in Grid Computing: A Modeling and Prediction Perspective
Experimental performance studies on computer systems, including Grids, require deep understandings on their workload characteristics. The need arises from two important and closel...
Hui Li
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