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DATE
2009
IEEE
86views Hardware» more  DATE 2009»
14 years 1 months ago
A power-efficient migration mechanism for D-NUCA caches
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...
Alessandro Bardine, Manuel Comparetti, Pierfrances...
JPDC
2007
60views more  JPDC 2007»
13 years 6 months ago
The impact of wrong-path memory references in cache-coherent multiprocessor systems
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
IPPS
2006
IEEE
14 years 1 months ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
SAINT
2003
IEEE
14 years 8 days ago
A Generalized Target-Driven Cache Replacement Policy for Mobile Environments
Caching frequently accessed data items on the client side is an effective technique to improve the system performance in wireless networks. Due to cache size limitations, cache re...
Liangzhong Yin, Guohong Cao, Ying Cai
ASPLOS
1992
ACM
13 years 11 months ago
Non-Volatile Memory for Fast, Reliable File Systems
Given the decreasing cost of non-volatile RAM (NVRAM), by the late 1990's it will be feasible for most workstations to include a megabyte or more of NVRAM, enabling the desig...
Mary Baker, Satoshi Asami, Etienne Deprit, John K....