37 search results - page 5 / 8 » Buffer Insertion for Noise and Delay Optimization |
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...
DAC
1997
ACM
14 years 21 days ago
1997
ACM
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
ISPD
1997
ACM
14 years 21 days ago
1997
ACM
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...