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IEEEPACT
2002
IEEE
14 years 3 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
ICCAD
2009
IEEE
133views Hardware» more  ICCAD 2009»
13 years 7 months ago
A parallel preconditioning strategy for efficient transistor-level circuit simulation
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
Heidi Thornquist, Eric R. Keiter, Robert J. Hoekst...
PDP
2011
IEEE
13 years 1 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
HPCA
2012
IEEE
12 years 5 months ago
Improving write operations in MLC phase change memory
Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. In particular, multi...
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002, B...
ASPLOS
2009
ACM
14 years 10 months ago
Dynamic prediction of collection yield for managed runtimes
The growth in complexity of modern systems makes it increasingly difficult to extract high-performance. The software stacks for such systems typically consist of multiple layers a...
Michal Wegiel, Chandra Krintz